There are high-functionality devices made up of a variety of interconnected circuit blocks, typified by wireless devices. With the development of process technology in recent years, it is possible to fabricate such high-functionality devices as a one-chip IC (Integrated Circuit).
A filter circuit, which is one of the circuit blocks making up a wireless device, serves to remove signals in unwanted frequency bands and to allow signals to pass in desired frequency bands. Therefore, the filter circuit is required to have frequency characteristics of higher accuracy than the other circuit blocks.
If a filter circuit is to achieve cutoff characteristics of secondary or higher order as a filter function, then the filter needs to use an active filter having active elements in its filter section. The active filter often comprises a gm-C filter which takes up a small area and which operates at high speed. The gm-C filter comprises a voltage-to-current converting circuit having active elements and a capacitor. The gm-C filter usually includes an automatic adjusting circuit for adjusting the deviation between designed values and actual frequency characteristics due to production process variations. The automatic adjusting circuit performs two adjusting processes, i.e., cutoff frequency adjustment (F-tune) and Q factor adjustment (Q-tune).
The F-tune refers to the following correcting technology. The cutoff frequency of the filter section is determined by the parameters of a capacitance value and a conversion gain of the capacitor and the voltage-to-current converting circuit of the filter section. If these parameters are shifted from designed values due to production process variations, then the actual value of the cutoff frequency is also shifted from the designed value. The F-tune is the technology for correcting the shift.
The Q-tune refers to the following correcting technology. The capacitor and the voltage-to-current converting circuit of the filter section include a parasitic resistance which is difficult to estimate sufficiently by way of simulations. The parasitic resistance tends to degrade the gain of the filter section from the designed value particularly in the vicinity of the cutoff frequency. The Q-tune is the technology for correcting the degradation of the gain.
Generally, the F-tune is frequently carried out. However, the Q-tune is not usually performed for filter circuits having gradual cutoff characteristics of fourth or lower order which can satisfy specifications according to many communication systems. The reason for this is that the filter circuits having gradual cutoff characteristics have a small gain sensitivity to the parasitic resistance in the vicinity of the cutoff frequency and are not essentially susceptible to gain degradations. However, filter circuits having sharp cutoff characteristics of fifth or higher order have a large gain sensitivity to the parasitic resistance in the vicinity of the cutoff frequency and are susceptible to gain degradations. In such a case, it is necessary to perform the Q-tune.
The effect that the parasitic resistance of the filter section of a second-order low-pass filter circuit on the gain will be described below.
FIG. 1 is a block diagram showing the configuration of a filter section using a gm-C filter in a second-order low-pass filter circuit.
In FIG. 1, voltage-to-current converting circuits (Gm1 through Gm4) 47 through 50 are circuits for outputting a current depending on an input voltage, and have respective conversion gains gm1 through gm4. Capacitors (C1, C2) 51, 52 have respective capacitance values c1, c2. Parasitic resistors (Gpar1, Gpar2) 53, 54 that are parasitically added to the respective nodes have parasitic conductances gpar1 gpar2, respectively.
Usually, the parasitic conductance of a parasitic resistor is substantially equal to the sum of the output conductances of voltage-to-current converting circuits which are connected to each node. The degree to which the parasitic conductance affects the gain of the filter section is clarified by a transfer function according to the following equation 1:
                              T          ⁡                      (            s            )                          =                              -                                                            gm                  1                                ⁢                                  gm                  2                                                                              C                  1                                ⁢                                  C                  2                                                                                        s              2                        +                                          (                                                                                                    gm                        4                                            +                                              g                                                  par                          ⁢                                                                                                          ⁢                          1                                                                                                            C                      1                                                        +                                                            g                                              par                        ⁢                                                                                                  ⁢                        2                                                                                    C                      2                                                                      )                            ⁢              s                        +                                                  ⁢                                                                                gm                    2                                    ⁢                                      gm                    3                                                  +                                                      (                                                                  gm                        4                                            +                                              g                                                  par                          ⁢                                                                                                          ⁢                          1                                                                                      )                                    ⁢                                      g                                          par                      ⁢                                                                                          ⁢                      2                                                                                                                    C                  1                                ⁢                                  C                  2                                                                                        [                  Equation          ⁢                                          ⁢          1                ]            
Equation 1 indicates that as the parasitic conductance is greater, the gain becomes degraded.
The gain degradation at a cutoff frequency ω0 is clarified by the following equation 2 which represents the gain at the cutoff frequency ω0:
                                          A            v                    ⁡                      (                          ω              0                        )                          =                                                        T              ⁡                              (                                  ω                  0                                )                                                          =                                                                      gm                  1                                ⁢                                  gm                  2                                                                              C                  1                                ⁢                                  C                  2                                                                                    (                                                                                                    gm                        4                                            +                                              g                                                  par                          ⁢                                                                                                          ⁢                          1                                                                                                            C                      1                                                        +                                                            g                                              par                        ⁢                                                                                                  ⁢                        2                                                                                    C                      2                                                                      )                            ⁢                              ω                0                                                                        [                  Equation          ⁢                                          ⁢          2                ]            
ω0 is expressed by the following equation 3:
                              ω          0                =                                                                              gm                  2                                ⁢                                  gm                  3                                            +                                                (                                                            gm                      4                                        +                                          g                                              par                        ⁢                                                                                                  ⁢                        1                                                                              )                                ⁢                                  g                                      par                    ⁢                                                                                  ⁢                    2                                                                                                      C                1                            ⁢                              C                2                                                                        [                  Equation          ⁢                                          ⁢          3                ]            
If gm2 and gm3 and c1 and c2 are designed substantially equally, then equation 2 is expressed by equation 4 below. gm2 is approximated to a value that is sufficiently larger than gpar2.
                                          A                          v              ⁢                                                          ⁢              1                                ⁡                      (                          ω              0                        )                          =                              gm            1                                              (                              1                +                α                            )                        ·                          gm              4                                                          [                  Equation          ⁢                                          ⁢          4                ]            
where α is expressed by the following equation (5):
                    α        =                                            g                              par                ⁢                                                                  ⁢                1                                      +                          g                              par                ⁢                                                                  ⁢                2                                                          gm            4                                              [                  Equation          ⁢                                          ⁢          5                ]            
Equation 4 indicates that the rate at which 1+α increases and the rate at which the gain decreases are equal to each other.
The transfer function of a high-order filter circuit includes, as factors, a plurality of transfer functions of the second-order low-pass filter circuit indicated by equation 1. As the order becomes higher, gm4 of each of the transfer functions usually becomes smaller. Therefore, the value of α becomes greater as indicated by equation 5, and the gain is greatly degraded as indicated by equation 4.
The Q-tune is generally realized by correcting the gain of a replica of a portion of the circuit blocks that make up the filter section. In other words, it is possible to correct the gain of the filter section by imparting a corrective signal generated to correct the gain of the replica to the filter section. It is possible to minimize the deviation between the gains of the filter section and the replica due to production process variations by sufficiently holding the filter section and the replica closely to each other in the chip layout.
In the replica and the filter section, the parasitic conductance which brings out the gain degradation essentially comprises the output conductance of each of the voltage-to-current converting circuits of the replica and the filter section.
In the replica, a negative resistor is connected to the output node of each voltage-to-current converting circuit of the replica. A corrective signal is generated such that the sum of the negative resistance and the output conductance of each voltage-to-current converting circuit is nil, and applied to the negative resistor.
In the filter section, the corrective signal generated by the replica is applied to a negative resistor connected to the output node of each voltage-to-current converting circuit of the filter section. As is the case with the replica, the sum of the negative resistance and the output conductance of each voltage-to-current converting circuit is adjusted to nil. The gain of the filter section is thus corrected.
A circuit for correcting the gain of the replica is generally of such a configuration that the output amplitude of the replica which is supplied with an input AC signal from an external source is detected by a peak detector or the like, and the negative resistor is controlled to equalize the detected value to a desired value.
A filter circuit disclosed in Patent document 1 incorporates the above configuration directly into a filter section for correcting the gain, without the need for a replica. The arrangement of the filter circuit disclosed in Patent document 1 is shown in FIG. 2.
The filter circuit shown in FIG. 2 comprises voltage-to-current converting circuits 55, 56 of the differential current output type, load resistor (NIC) 57, peak detector 58, and digital-to-analog converter (DAC) 59, and register 60. 61 through 63 denote standard currents.
For correcting the gain of the filter circuit shown in FIG. 2, the output amplitude of voltage-to-current converting circuit 56 which is supplied with an input AC signal from an external source is detected by peak detector 58, and negative resistor 57 is controlled based on the result of a comparison between the detected amplitude value and a preset amplitude value from register 60.
FIG. 3 is a diagram of the frequency characteristics of a second-order low-pass filter circuit, showing characteristic curves plotted when the value of α is positive, nil, and negative.
The characteristic curve plotted when the value of α is nil is a desired filter characteristic curve. Since the negative resistance cancels out the parasitic conductance according to the Q-tune, the value of α is adjusted to a value that is nearly nil, adjusting the filter section to desired frequency characteristics. The adjusting accuracy mainly depends on the detecting accuracy of the peak detector for detecting the output amplitude. If the detecting accuracy of the peak detector is low, then the adjusting process is completed when the value of α is significantly different from nil.
Non-patent document 1 discloses a filter circuit which uses no peak detector. The arrangement of the filter circuit disclosed in Non-patent document 1 is shown in FIG. 4.
In the filter circuit shown in FIG. 4, the difference between the amplitude of a reference signal input to replica (Master Biquad) 65 and the amplitude of an AC signal output from replica 65 is detected, and the filter circuit is controlled to make the detected value nil. The difference is detected by differential device 66 and multiplier 67. Therefore, the filter circuit does not need a peak detector.
Since the peak detector is difficult to fabricate to a nicety, the configuration shown in FIG. 4 makes it possible to achieve the Q-tune with high accuracy.
As described above, the filter circuits of the background art need to detect the amplitude of a signal input to the filter section or its replica.
As disclosed in Patent document 1, however, in order to detect the amplitude of the AC signal highly accurately with the peak detector, the linearity of the circuit operation of the peak detector needs to be increased. Generally, the increased linearity requires a complex circuit for performing linearity compensation, with the results that the filter circuit consumes increased electric power and takes up an increased chip area.
As disclosed in Non-patent document 1, in order to increase the accuracy with which to detect the amplitude of the AC signal with the differential device and the multiplier, the linearity of the circuit operation of the differential device and the multiplier also needs to be increased. The increased linearity also makes the filter circuit consume increased electric power and take up an increased chip area, as is the case with the filter circuit requiring increased accuracy of the peak detector.
If the AC signal component input to the peak detector leaks out into a Q-tune control signal line of the filter circuit, then the operation of the filter circuit becomes unstable. One approach to stably operate the filter circuit would be to insert a new circuit for removing the AC signal component that has leaked out into the control signal line. This approach would also cause the filter circuit to consume increased electric power and take up an increased chip area.
As described above, it has been difficult for the filter circuits described in the background art to achieve low electric power consumption, to take up a small chip area, and to achieve highly accurate Q-tune.
To solve the above problems, it is necessary to have an automatic output conductance adjusting circuit for automatically adjusting the output conductance of a voltage-to-current converting circuit of a filter section with high accuracy, while making a filter circuit consume low electric power and take up a small chip area.
Patent document 1: JP-A No. 6-342561 (FIG. 1)
Non-patent document 1: Jan-Michael Stevenson and Edgar Sanchez-Sinencio, “A Practical Quality Factor Tuning Scheme for IF and High-Q Continuous-Time Filters”, ISSCC Dig. Tech. Papers, February, 1998, pp. 218-219.